During the design of an application specific integrated circuit (ASIC) or system-on-chip (SOC), design for test (DFT) and automatic test pattern generation (ATPG) methodologies are typically used to develop a test sequence that, when applied to the ASIC or SOC, can detect potential failures of the ASIC or SOC. After the ASIC or SOC has been manufactured, it can be placed into scan mode, which forces all the flip-flops in the device to be connected in a simplified fashion, and these test sequences can be used to test all the flip-flops, as well as to trace failures to specific flip-flops.
Data theft from scan mode is an emerging challenge. While the chips are in functional mode, the registers may contain important identification details. Critically private data such as passwords, fingerprints, iris scans, IDs and the like can be stolen from hardware by changing the chip mode to scan mode and extracting the data from the scan mode output. Chip enabled credit cards and smart cards are particularly vulnerable to such data thefts, and even automotive applications can be susceptible to identification data thefts.